Develop the NVMe Verification environment by Verilog / System Verilog
Formal verification flow build-up and checking.
Verification and debug the high speed interface.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Familiar with high speed (PCIE, USB, MIPI, SATA) protocol and architecture
Knowledge and design experience of design verification such as UVM and system Verilog / Verilog.
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